1. Field of the Invention
The present disclosure relates to configurable logic cells, and, more particularly, to a processor with a combinatorial logic peripheral, a configurable logic cell incorporated in a microprocessor and operating independently thereof, a configurable logic cell allowing software access to internal configuration and signal paths in an integrated circuit device, a configurable logic cell with real-time configuration control, and a configurable logic cell incorporating one or more logic functions.
2. Description of the Related Art
A processor system, such as a Reduced Instruction Set Computing (RISC) processor system, can include a microprocessor core and a plurality of peripherals.
The operation of a microprocessor is, from time to time, halted intentionally in order to (a) reduce power consumption (e.g., sleep or hibernate), or (b) allow inspection of internal registers by 3rd party logic (e.g., debug freeze). In those instances, peripheral devices are generally also halted, either to simplify the logic interface, or to allow a “present state” to be captured for inspection.
Devices such as Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD) provide configurable logic cells. Generally speaking, the design of the logic must explicitly provide for software inputs using registers, address buses, and other conventional microprocessor interface techniques, requiring additional FPGA resources be assigned to this feature. These conventional FPGA and PLD logic cells must be configured by the user, and that configuration remains static while the cell is in service.
FPGAs and PLDs provide configurable logic cells that are generally based on D flip-flop technology. While this is adequate for general purpose use and automated logic configuration, it does not always lead to a minimal circuit implementation solution.
As such, there is a need for improved systems and methods for providing configurable logic devices.